High Speed Transceiver Demo Designs For Current and Older Families

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Contents

Stratix 10 GX

Script with useful procedures for use in system console for Stratix 10 H-Tile ES1 and beyond

  • UPDATED (19/10/2017)

                http://www.alterawiki.com/wiki/File:ttk_helper_s10.tcl V2.1 (19/10/2017)

Transceiver Toolkit Designs and Link Tuning Test Designs

  • UPDATED (15/11/2017) Stratix 10 GX SI Board (H-Tile ES1): 64 Channel TTK design with all channels at 25 Gbps using 4 PHY's with Nios system + EyeQ + temperature and voltage measurement + internal noise logic + PMA sweep

                http://www.alterawiki.com/wiki/File:Stratix10_SIBoard_64Ch_Nios_Embedded_Prbs_HTile_26Gbps.zip (17.1 B240)

  • (10/07/2017) Stratix 10 GX SI Board (H-Tile ES1): 96 Channel TTK design with all channels at 12.5 Gbps using 4 PHY's with Nios system + EyeQ + temperature and voltage measurement.

                http://www.alterawiki.com/wiki/File:Stratix10_SIBoard_96Ch_Nios_Embedded_Prbs_HTile.zip (17.1 IR.2 B50)

  • (29/05/2017) Stratix 10 GX SI Board (L-Tile ES1): 96 Channel TTK design using 4 PHY's with Nios system + EyeQ + temperature and voltage measurement + ODI Acceleration enabled

                http://www.alterawiki.com/wiki/File:Stratix10_SIBoard_96Ch_Nios_Embedded_Prbs.zip (17.1 IR.1 B46)

  • (05/04/2017) Stratix 10 GX PCIe Development kit(L-Tile ES1): 72 Channel TTK design with Nios system + EyeQ + temperature and voltage measurement.

                http://www.alterawiki.com/wiki/File:Stratix10_Devkit_72Ch_Nios_Embedded_Prbs.zip (17.0 IR3 B182 patch 0.01IR3 + 0.02IR3)

KR-FEC

  • Updated (25/10/2017) Stratix 10 GX SI Board (H-Tile ES1): 8 Channel Multi PRBS Test design at 25.8 Gbps using KR-FEC (Tested up to 30 Gbps with 5 meter DAC Cable) (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:Stratix10_SIBoard_8Ch_Multi_Prbs_KRFEC_Htile_26Gbps.zip (17.1 CB B235)

Superlite II V3

  • NEW (03/11/2017) Stratix 10 GX SI Board (H-Tile ES1): Superlite II V3 demo design using 8 lanes at 25.78125 Gbps routed to the 2 QSFP28 modules (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:S10_SIBoard_SuperliteII_V3_8_Lanes_26G.zip (17.1 CB B235)

  • Updated (17/10/2017) Stratix 10 GX SI Board (H-Tile ES1): Superlite II V3 demo design using 4 lanes at 12.5 Gbps routed to FMC connector A (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:S10GX_SIBoard_SuperliteII_V3_4_lanes_12.5Gbps_FMC.zip (17.1 CB B235)

Superlite II Synchronous

  • (13/04/2017) Stratix 10 GX SI Board (L-Tile ES1): Superlite II Synchronous demo design to transport fully transparently a 25.6 Gbps datastream using 4 lanes at 8 Gbps routed to FMC connector A (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:S10GX_SIBoard_SuperliteII_Synchronous_4_lanes_8Gbps.zip (17.0 IR3 B182 patch 0.01IR3 + 0.02IR3 + 0.08IR3)


Ultralite II Asynchronous

  • UPDATED (11/10/2017) Stratix 10 GX SI Board (H-Tile ES1): Ultralite II Asynchronous demo design to transport 50 Gbps data using 4 lanes at 12.5 Gbps routed to FMC connector A (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:S10_SI_Board_4Ch_ULII_FMC.zip (17.1 CB B235)

Link Tuning Test design L-Tile ES1 (Old, not recommended to use any longer)

  • (13/04/2017) Stratix 10 GX SI Board (L-Tile ES1): 4 Channel Link Tuning Test design (12.5 Gbps per lane) using 3 methods : ODI workaround, PMA sweep and automatic AC gain optimization (Backplane and chip-to-chip) (note that this design is still Work In Progress), temperature measurement added for core and transceiver tile

                http://www.alterawiki.com/wiki/File:Stratix10_SIBoard_4Ch_Multi_Prbs_Link_Tuning.zip (17.0 IR3 B182 patch 0.01IR3 + 0.02IR3 + 0.08IR3)


Arria10 GX

Script with useful procedures for use in system console

  • (18/11/2016) This script is the most up to date version and replaces the ttk_helper.tcl script found in the projects below, it also contains an automatic AC gain optimization algorithm

                http://www.alterawiki.com/wiki/File:ttk_helper.tcl V9.2 (18/11/2016)

Superlite II V3

  • (13/04/2017) Arria10 GX SI Board : Superlite II V3 Design using 4 lanes at 10.3125 Gbps routed to QSFP+ module (V3 offers handshaking and Flow Control (ON/XOFF)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_V3_4_lanes_10Gbps_QSFP+.zip (16.1.2 B203)

Superlite II Synchronous

  • (20/04/2017) Arria10 GX SI Board : Superlite II Synchronous Design using 4 lanes at 8 Gbps all clocked from one 100 Mhz clock (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_Synchronous_4_lanes_8Gbps.zip (16.1.2 B203)

Link Tuning Test designs

  • (24/11/2016) Arria10 GX SI Board (Production): 4 Channel Link Tuning Test design (12.5 Gbps per lane) using 3 methods : ODI workaround, PMA sweep and automatic AC gain optimization (Backplane and chip-to-chip)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_Multi_Prbs_with_ODI_Workaround.zip (16.1 B196)

Seriallite II with KR-FEC

  • (11/07/2016) Arria10 GX SI Board : Seriallite II with FREE KR-FEC backplane demo design using 4 lanes at 12.5 Gbps (incl. TTK functionality and ODI)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_Seriallite_4_Lanes_12_5Gbps_soft8b10b_KRFEC.zip (16.0.1 B211)

Superlite II Video

  • (01/03/2016) Arria10 GX SI Board (ES3)): Superlite II Video demo design transporting transparently Video and Aux Data across a 10.3 Gbps link

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_Video_1_Lane.zip (15.1.2 B193)

Superlite V3

  • (11/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V3 demo design with 1 lane at 2.5 Gbps (V3 offers handshaking and Flow Control (ON/XOFF)

                http://www.alterawiki.com/wiki/File:A10GX_Devkit_Superlite_V3_1_lane_2500Mbps.zip (15.1.2 B192)

  • (11/02/2016) Arria10 GX SI Board (ES3): Superlite V3 demo design with 1 lane at 2.5 Gbps (V3 offers handshaking and Flow Control (ON/XOFF)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_Superlite_V3_1_lane_2500Mbps.zip (15.1.2 B192)

Superlite V2

  • (05/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V2 demo design with 1 lane at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:A10GX_Devkit_Superlite_V2_1_lane_2500Mbps.zip (15.1.2 B192)

  • (04/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V2 demo design with 4 lanes at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:A10GX_Devkit_Superlite_V2_4_lanes_2500Mbps.zip (15.1.2 B192)

Backplane Test designs with optional KR FEC + Transceiver Toolkit Support + ADME

  • (07/01/2016) Arria10 GX SI Board (ES3): Multi PRBS Backplane demo design with optional KR-FEC (4 lanes at 16 Gbps) (the design uses dynamic reconfiguration of the channel to switch between KR-FEC mode and normal mode)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_Multi_Prbs_ES3_16Gbps_with_optional_KRFEC.zip (15.1.1 B189)

Superlite II with KR-FEC at 25.8 Gbps

  • (13/11/2015) Arria10 GX SI Board : Superlite II with FREE KR-FEC demo design using 4 GT lanes at 25.781 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_with_KRFEC_4_lanes_25.8Gbps.zip (15.1 B185)

Superlite II V2 with KR-FEC

  • (12/11/2015) Arria10 GX SI Board : Superlite II V2 with FREE KR-FEC backplane demo design using 4 lanes at 16 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_V2_with_KRFEC_4_lanes_16Gbps_backplane.zip (15.1 B185)

Seriallite II

  • (16/09/2015) Arria10 GX PCIe Development Kit (ES2): Seriallite II demo design with 4 lanes at 12.5 Gbps using 8b10b soft PCS (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_Seriallite_4_Lanes_12_5Gbps_soft8b10b_ES2.zip (15.0.2 B153)

  • (22/05/2015) Arria10 GX PCIe Development Kit (ES2): Seriallite II demo design with 4 lanes at 10 Gbps (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_Seriallite_4_Lanes_10Gbps_ES2.zip (15.0.1 B147)

  • (14/01/2015) Arria10 GX SI Board: Seriallite II demo design with 4 lanes at 10 Gbps (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_Seriallite_4_Lanes_10Gbps_14_1.zip (14.1A10s B652)

Dynamic Reconfiguration

  • (23/06/2016) Arria10 GX SI Board (ES3): 4 Ch Dynamic Reconfiguration Demo Design Using Data rate reconfiguration and TX PLL clock switching. (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_TXPLL_and_datarate_reconfiguration.zip (16.0.1 B218)

  • (06/07/2015) Arria10 GX PCIe Development Kit (ES2): 4 Ch Dynamic Reconfiguration Demo Design Using Fast Reconfig , using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_4Ch_DPRIO_3_datarates_DP_testcase_fast_reconfig.zip (15.0.1 B150)


  • (04/05/2015) Arria10 GX SI Board : 4 Ch Dynamic Reconfiguration Demo Design Using Fast Reconfig using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_DPRIO_3_datarates_DP_testcase_fast_reconfig.zip (15.0.1 B147)

  • (03/04/2015) Arria10 GX PCIe Development Kit : 4 Ch Dynamic Reconfiguration Demo Design Using Embedded Streamer and Dynamic fPLL Programming, using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_4Ch_DPRIO_3_datarates_DP_testcase.zip (15.0 CB B139)



Ultralite II Asynchronous

  • (12/05/2015) Arria10 GX PCIe Development Kit (ES2) : Ultralite II Asynchronous demo design to transport 50 Gbps data using 4 lanes at 12.5 Gbps (incl. TTK functionality and EyeQ)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_UltraliteII_Asynchronous_4_Lanes_12500Mbps_ES2.zip (15.0.1 B147)

  • (25/02/2015) Arria10 GX PCIe Development Kit : Ultralite II Asynchronous demo design to transport 40 Gbps data using 4 lanes at 10 Gbps (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_UltraliteII_Asynchronous_4_Lanes_10Gbps.zip

Transceiver Toolkit Designs

  • (23/11/2016) Arria10 GX SI Board Rev E4(Production): 24 Channel Transceiver Toolkit design at 12.5 & 10.3125 Gbps (QSFP+) using 3 Native PHY's (includes tcl file with multiple useful procedures)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_24Ch_TTK.zip (16.1 B196)

  • (27/01/2017) Arria10 GX PCIe Development Kit (Production):  : 12 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_12Ch_TTK.zip (16.1.1 B200)

  • (27/01/2017) Arria10 GX PCIe Development Kit (Production):  : 4 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_4Ch_TTK.zip (16.1.1 B200)

Ultralite

  • (03/07/2015) Arria10 GX PCIe Development Kit (ES2): Ultralite Synchronous demo design (80 ns Tx to Rx latency) to transport 96 Gbps data using 12 lanes at 10 Gbps (incl. TTK functionality)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_Ultralite_Synchronous_12_lanes.zip (15.0.1 B150)

  • (28/11/2014) Arria10 GX SI Board: Ultralite Synchronous demo design (80 ns Tx to Rx latency) to transport 32 Gbps data using 4 lanes at 10 Gbps

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_Ultralite_Synchronous_4_Lanes.zip (14.0A10s B578 0.03)

  • Arria10 GX SI Board: Ultralite Synchronous demo design (sub 100 ns Tx to Rx latency) to transport 100 Gbps data using 12 lanes at 10+ Gbps (not ported to board yet)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_Ultralite_Synchronous_12_Lanes.zip

PRBS Test designs with Transceiver Toolkit Support and ADME

 

  • (08/12/2015)Arria10 GX SI Board (ES3): Multi Prbs Demo design using 4 lanes at 10.3125 Gbps with one lane connected to the SFP+ module (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_Multi_Prbs_Native_PHY_SFP.zip (15.1 B185)

  • (24/12/2014) Arria10 GX SI Board: Multi Prbs Demo design using 10 lanes at 10.0 Gbps using ODI workaround and autosweep for optimum PMA settings using one reference clock only

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_10Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI_one_refclock.zip (14.0A10s B578 0.03)

  • (24/12/2014) Arria10 GX SI Board: Multi Prbs Demo design using 4 lanes at 10.0 Gbps using ODI workaround and autosweep for optimum PMA settings using one reference clock only

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI_one_refclock.zip (14.0A10s B578 0.03)

  • (28/11/2014) Arria10 GX SI Board: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps using ODI workaround and autosweep for optimum PMA settings

                http://www.alterawiki.com/wiki/File:Arria10_SIBoard_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI.zip (14.0A10s B578 0.03)

  • (24/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps using ODI workaround and autosweep for optimum PMA settings

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI.zip (14.0A10s B578 0.03)

  • (18/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 12 lanes at 10.3125 Gbps routed to FMC connector A (non-bonded)

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_12Ch_Multi_Prbs_Native_Phy_with_TTK_support_not_bonded.zip (14.0A10s B578 0.03)

  • (14/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps routed to FMC connector A

                http://www.alterawiki.com/wiki/File:Arria10_Devkit_4Ch_Multi_Prbs_Native_Phy_with_TTK_support.zip (14.0A10s B578 0.03)

Ultralite II Synchronous

  • Arria10 GX SI Board: Ultralite II Synchronous demo design to transport 100-120 Gbps data using 10 lanes at 10-12.5 Gbps (not ported to board yet)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_UltraliteII_Synchronous_10_Lanes.zip

Superlite II

  • Arria10 GX SI Board: Superlite II demo design using 10 lanes at 12.5 Gbps (not ported to board yet)

                http://www.alterawiki.com/wiki/File:A10GX_SIBoard_SuperliteII_10_Lanes.zip


Cyclone V GX

Seriallite II

  • (07/12/2015)Cyclone V GX Devkit: Seriallite II Demo Design Using 15.1 Megacore, 4 Lanes at 2.5Gbps

                http://www.alterawiki.com/wiki/File:CVGX_Devkit_Seriallite_4_Lanes_2500Mbps_Megacore.zip (15.1 B185)


Stratix V GT

Fixed Rate (PRBS)

  • Stratix V GT SI Board: 4 Channel Multi-PRBS at 25 Gbps with minimal TX skew

                http://alterawiki.com/wiki/File:GTV_SI_Board_4Ch_Multi_Low_Latency_skew_test.zip

  • Stratix V GT SI Board: 4 Channel Multi-PRBS at 25 Gbps

                http://www.alterawiki.com/wiki/File:GTV_SI_Board_4Ch_Multi_Prbs_Low_Latency_25Gbps.zip


Stratix V GX

Backplane with Temperature Tracking IP

  • (26/11/2015) Stratix V GX SI Board: 4 Channel 10.3125 Gbps Backplane demo design with Temperature Tracking IP

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_Temp_Tracking_Backplane.zip (15.0.2 B153)

Ultralite II

  • Stratix V GX SI Board: Ultralite II Synchronous demo design to transport 100-120 Gbps data using 10 lanes at 10-12.5 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_UltraliteII_Synchronous_10_Lanes.zip


  • Stratix V GX SI Board: Ultralite II Synchronous demo design to transport 50-60 Gbps data using 5 lanes at 10-12.5 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_UltraliteII_Synchronous_5_Lanes.zip

Oversampling

  • Stratix V GX SI Board: OC3 Oversampling design (5x) with recreation of recovered clock using fPLL and PI controller

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_1Ch_Multi_Prbs_155Mbps_Clock_Recovery.zip

DXAUI

  • Stratix V GX SI Board: DXAUI demo design using Native PHY and external DXAUI PCS

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_DXAUI_Demo.zip

Ultralite

  • Stratix V GX SI Board: Ultralite Synchronous demo design (sub 100 ns Tx to Rx latency) to transport 100 Gbps data using 12 lanes at 10+ Gbps

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_Ultralite_Synchronous_12_Lanes.zip

EyeQ, BERB and DFE

  • Stratix V GX SI Board: 4 Ch Multi-PRBS demo design illustrating EyeQ and BERB in 2D mode + One Time DFE + DVD and Slew Rate Control running at 14.1 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_EyeQ_BERB_2D_DFE_DCD_Slewrate_14Gbps.zip

  • Stratix V GX SI Board: 4 Ch Multi-PRBS demo design illustrating EyeQ and Berb in 2D mode + One Time DFE + DCD and Slew Rate Control

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_EyeQ_BERB_2D_DFE_DCD_Slewrate.zip

Superlite II

  • Stratix V GX SI Board: Superlite II V2 Packet Mode Demo Design: 11 Lanes at 12.5 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_SuperliteII_V2_Packet_Mode_11_Lanes.zip

  • Stratix V GX SI Board: Superlite II V2 Streaming Mode Demo Design: 11 lanes at 12.5 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SIBoard_SuperliteII_V2_11_Lanes.zip

  • Stratix V GX SI Board: Superlite II demo design: 5 Lanes at 11.3 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_Superlite_II_5_Lanes_11Gbps.zip

  • Stratix V GX SI Board: Superlite II Demo Design: 10 Lanes at 11.3 Gbps

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_Superlite_II_10_Lanes_11Gbps.zip

Dynamic Reconfiguration

  • Stratix V GX SI Board: 1 Ch Dynamic Reconfiguration Demo Design Using Direct Mode 3 to Reconfigure ATX PLL

                http://www.alterawiki.com/wiki/File:StratixV_SIBoard_1Ch_Multi_Prbs_DPRIO_2_SW_13_0_Direct_Mode_3_1_Refclk.zip

  • Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching and Dynamic fPLL Programming w/ independent Tx and Rx Operation Bonded Tx (DP++ testcase using MIF mode 1); 5.4, 2.7 and 1.62 Gbps Data Rates for DisplayPort, contiguous 1 Gbps .. 6 Gbps data rates for HDMI

                http://www.alterawiki.com/wiki/File:StratixV_SIBoard_4Ch_DPRIO_DPplusplus_TestCase_13_1_bonded.zip

  • Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching w/ independent Tx and Rx Operation Bonded Tx (DP++ testcase using MIF mode 1)

                http://www.alterawiki.com/wiki/File:StratixV_SIBoard_4Ch_DP_TestCase_4_datarates_12_1_Native_Phy_V2_bonded.zip

  • Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching with Independent Tx and Rx Operation (DP++ testcase using MIF mode 1)

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_DPRIO_4_datarates_DPplus_Testcase.zip

  • Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching with Independent Tx and Rx Operation (Displayport Testcase) (Using MIF mode 0)

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_DPRIO_3_datarates_DP_Testcase.zip

  • Stratix V GX SI Board: 1 Ch Dynamic Reconfiguration Demo Design Using MIF Streamer Mode 0 (reconfigure between 10.3125 Gbps and 8.5 Gbps) using LC PLL and Native PHY

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_1Ch_DPRIO_2_Datarates_MIF_Streaming.zip

  • Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_DPRIO_2_RefClock.zip

Seriallite II

  • Stratix V GX SI Board: Seriallite II Demo Design Using 13.0 Megacore, 4 Lanes at 2.5Gbps

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_Seriallite_4_Lanes_2500Mbps_Megacore.zip

  • Stratix V GX SI Board: Seriallite II Demo Design Using 12.1 Megacore, 4 lanes at 10.3125Gbps

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_Seriallite_4_Lanes_10Gbps_Megacore.zip

  • Stratix V GX SI Board: Seriallite II Demo Design 4 lanes at 10.3125Gbps or 16x External Reference Clock Frequency (Not recommended-for new designs see Megacore design)

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_Seriallite_4_Lanes_10Gbps.zip

  • Stratix V GX Development Kit: Seriallite II Demo Design: 4 Lanes at 6.25Gbps

                (Not recommended-for new designs see Megacore design)
                http://www.alterawiki.com/wiki/File:GXV_Devkit_Seriallite_4_Lanes_6250Mbps.zip


Fixed Rate (PRBS)

  • Stratix V GX SI Board: 10 Channel Multi-PRBS at 10.3125Gbps or 16x External Reference Clock Frequency

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_10Ch_Multi_Prbs_Low_Latency.zip

  • Stratix V GX SI Board: 1 Channel XFP Multi-PRBS at 10.3125Gbps w/ Reverse Parallel Loopback

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_1Ch_Multi_Low_Latency_XFP.zip

  • Stratix V GX SI Board: 1 Channel XFP Multi-PRBS at 10.3125Gbps w/ reverse parallel loopback and XFP RefClock

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_1Ch_Multi_Low_Latency_XFP_with_refclk_XFP.zip

  • Stratix V GX SI Board: 1 Channel SMA Multi-PRBS at 10.3125Gbps w/ Reverse Parallel Loopback

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_1Ch_Multi_Low_Latency_SMA.zip

  • Stratix V GX SI Board: 4 Channel Multi-PRBS at 10.3125Gbps or 16x External Reference Clock Frequency

                http://www.alterawiki.com/wiki/File:GXV_SI_Board_4Ch_Multi_Low_Latency.zip

  • Stratix V GX Development Kit: 4 Channel Multi-PRBS at 6.25Gbps (Onboard 156.25Mhz Oscillator)

                http://www.alterawiki.com/wiki/File:GXV_Devkit_4Ch_Multi_Prbs_6250Mbps.zip



Stratix IV GX

Recovered Clock Generation and System Clock Generation using GPLL (no cascading)

  • Stratix IV GX SI board: 1 Channel 64b66 encoded design at 6.25Gbps with creation of recovered clock and system clock through GPLL

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_1Ch_64b66b_Clock_Recovery_GPLL.zip

Recovered Clock Generation for Oversampling Based Designs

  • Stratix IV GX SI board: 1 Channel Multi-PRBS design at OC-3 rate using oversampling and creation of recovered clock through GPLL

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_1Ch_Multi_Prbs_155Mbps_Clock_Recovery.zip

AEQ and EyeQ

  • Stratix IV GX SI board: 6 Channels Multi-PRBS design (using socket oscillator) with AEQ and EyeQ enabled

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_6Ch_Multi_Prbs_Socket_Oscillator_EyeQ_ADCE.zip

EyeQ

  • Stratix IV GX SI board : 6 Channels Multi Prbs design (using socket oscillator) with EyeQ

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_6Ch_Multi_Prbs_Socket_Oscillator_EyeQ.zip

SoftCDR & LVDS_PHY

  • Stratix IV GX PCIe Board: 4Ch LVDS_PHY_SoftCDR Demo at 1.25Gbps per Channel

                http://www.alterawiki.com/wiki/File:SIVGX_DevKit_LVDS_Phy_1250Mbps_SoftCDR_4Ch_SFP.zip


Aurora

  • Stratix IV GX SI board: Aurora demo Design : 1 lane at 2.5Gbps

                http://www.alterawiki.com/wiki/File:GXIV_SI_Board_Aurora_1_Lane_2500Mbps.zip

SFI5.1

  • Stratix IV GX SI board: 17 Channel Multi Prbs at 3.125Gbps using SFI5.1

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_17Ch_Multi_Prbs_3125Mbps_16bit_SFI51_Implementation.zip

XAUI

  • Stratix IV GX SI board: XAUI Demo Design

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_XAUI_Demo.zip

Dynamic Reconfiguration

  • Stratix IV GX SI board: Dynamic Reconfigurable Demo Design from XAUI <=> DXAUI

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_DXAUI_XAUI_Demo.zip

  • Stratix IV GX SI board: Dynamic Reconfigurable Demo Design from XAUI <=> GbE <=> GIG3

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_XAUI_GbE_GIG3.zip

  • Stratix IV GX SI board: 1Ch Dynamic Reconfiguration (Multi Rate Sonet, GbE, GIG3, FC-4 w/ 4 Input Clocks)

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_1Ch_Multirate_Sonet_GbE_FC4_4_input_clocks.zip

  • Stratix IV GX SI board: 2Ch Dynamic Reconfiguration (Multi Rate Sonet, GbE, GIG3, FC-4 w/ 4 Input Clocks)

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_2Ch_Multirate_Sonet_GbE_FC4_4_input_clocks.zip

Synchronous

  • Stratix IV GX SI board: 20Gbps Synchronous Demo 4 Scrambled Lanes at 5Gbps w/ Simple Training and Deskew

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Synchronous_4_Channels_5Gbps.zip

Seriallite II

  • Stratix IV GX Devkit: Seriallite II Demo Design Using LVDS: 4 lanes at 1.25Gbps

                http://www.alterawiki.com/wiki/File:GXIV_DevKit_SerialliteII_LVDS_4Ch_1250Mbps.zip

  • Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 6.25Gbps using PMA Only Channels

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Seriallite_4_Lanes_6250Mbps_PMA_Only.zip

  • Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 6.25Gbps (Onboard 312.5Mhz XO)

                http://www.alterawiki.com/wiki/File:GXIV_SI_Board_Seriallite_4_Lanes_6250Mbps.zip

  • Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 8.5Gbps with external 8b10b PCS (Onboard 425Mhz XO)

                http://www.alterawiki.com/wiki/File:GXIV_SI_Board_Seriallite_4_Lanes_8500Mbps.zip

  • Stratix IV GX SI board: Seriallite II Demo Design - 4 lanes at 8.5Gbps with internal 8b10b (Onboard 425 Mhz XO)

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Seriallite_4_Lanes_8500Mpbs.qar
                (Note: The link above is only the Quartus II archive, for documentation please see the above 6.25Gbps design.)

SuperLite V2

  • Stratix IV GX SI board: Superlite V2 demo Design: 2 lanes at 4Gbps with Avalon ST Transmit Interface

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Superlite_v2_2_Lanes_4000Mbps_Avalon_ST.zip


SuperLite

  • Stratix IV GX SI Board: SuperLite Demo Design: 6 lanes at 6.25Gbps using embedded PCS in ALTGX

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Superlite_6_Lanes_6250Mbps_PCS.zip

  • Stratix IV GX SI Board: SuperLite Demo Design: 2 lanes at 4Gbps using embedded PCS in ALTGX

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Superlite_2_Lanes_4000Mbps.zip

  • Stratix IV GX SI Board: SuperLite Demo Design: 2 lanes at 6.25Gbps using PMA only channels or mixed mode

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Superlite_2_Lanes_6250Mbps_PMA_and_MIX.zip

  • Stratix IV GX SI Board: SuperLite Demo Design: 4 lanes at 8.5Gbps (Onboard 450Mhz XO)

                http://www.alterawiki.com/wiki/File:GXIV_SIBoard_Superlite_4_Lanes_8500Mbps.zip


ArriaV GX

Oversampling

  • (05/01/2016) ArriaV GX Starterkit : 4 Channels Multi Prbs at 500 Mbps using 5x oversampling with 10000 ppm difference between Tx and Rx

                http://www.alterawiki.com/wiki/File:AV_Starter_Kit_4Ch_Multi_Prbs_5x_oversampling_500Mbps.zip (15.1.1 B189)

fPLL as TxPLL

  • ArriaV GX Starterkit: 4 Channels Multi-PRBS at 3.125Gbps using fPLL as TxPLL

                http://www.alterawiki.com/wiki/File:AV_Starter_Kit_4Ch_Multi_Prbs_fPLL_as_TxPLL.zip

Dynamic Reconfiguration

  • ArriaV GX Starterkit: 4 Ch Dynamic Reconfiguration demo Design with independent Tx and Rx operation and bonded Tx (DP testcase using MIF mode 1)

                http://www.alterawiki.com/wiki/File:AV_Starter_Kit_4Ch_DP_TestCase_3_datarates_bonded.zip

Superlite

  • ArriaV GX Starterkit: Superlite Demo Design - 4 lanes at 3.125Gbps

                http://www.alterawiki.com/wiki/File:AV_Starter_Kit_Superlite_4_Lanes_3125Mbps.zip

Fixed Rate (PRBS)

  • ArriaV GX Starterkit : 4 Channels Multi-PRBS at 3.125Gbps using the HSMC Connector

                http://www.alterawiki.com/wiki/File:AV_Starter_Kit_4Ch_Multi_Prbs.zip

Demo Designs for Older Families and Complete List of all Demo designs

The complete list of demo designs as of July 25th 2014 including the demo designs for the older families can be found here :
                File:High Speed Demo Designs July 25th 2014.doc

© 2014 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not
supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,
misleading or inaccurate.


 

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