I2C (OpenCores)

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Overview

This is a simple port of the OpenCores I2C component.  A top level wrapper was created as well as some simple drivers . 


Downloads

The folowing is compatible with 9.1

Download opencores_i2c.zip


The following was taken from the above and has been updated for 12.0 and QSys.  (Note that the component name was changed from opencores_i2c (used in the 9.1 version above) to i2c_opencores.) Also note that the _sw.tcl file in the v13.0 zip file uses the wrong naming convention, it uses the old name of opencores_i2c throughout the tcl assignments when it should use the new name of i2c_opencores to match all other files in the v13.0 zip. Failing to fix this in the v13.0 zip results in the driver not being loaded during BSP generation.

Download I2c_opencores_12.0.zip

Updated for 13.0 Download i2c_opencores_v13.0.zip

 

Qsys 14.0 or Newer

For Qsys 14.0 or newer you may get an error in Qsys stating that the export settings need to be unique. To fix this, edit the _hw.tcl file as follows:

replace this code:

  # 
  # connection point export
  # 
  add_interface export conduit end
  set_interface_property export associatedClock ""
  set_interface_property export associatedReset ""
  set_interface_property export ENABLED true
  set_interface_property export EXPORT_OF ""
  set_interface_property export PORT_NAME_MAP ""
  set_interface_property export SVD_ADDRESS_GROUP ""
  add_interface_port export scl_pad_io export Bidir 1
  add_interface_port export sda_pad_io export Bidir 1

with this code:

  # 
  # connection point export
  # 
  add_interface export conduit end
  set_interface_property export associatedClock ""
  set_interface_property export associatedReset ""
  set_interface_property export ENABLED true
  set_interface_property export EXPORT_OF ""
  set_interface_property export PORT_NAME_MAP ""
  set_interface_property export SVD_ADDRESS_GROUP ""
  add_interface_port export scl_pad_io scl Bidir 1
  add_interface_port export sda_pad_io sda Bidir 1

Arria-10, Quartus 15.0 SDA/SCL Bidir Warning 12620

Arria-10 compiles with bidirectional pins requires the /*synthesis keep*/ directive. See this link for more information and to resolve the issue: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01262015_264.html (Note that after applying the workaround, the warnings are still issued during the Quartus compile. Use the post fitting technology viewer to verify the correct signal is connected to the output enable. If the directive is not used the constant zero will erroneously be tied to the output enable when it should be tied to the input) (Problem exists in Quartus 15.0.0.145 and earlier for Arria-10)


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