New Qsys Issues
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Overview
The purpose of this page is to keep an active list of Qsys issues and workarounds over the first few releases of the tool in the Quartus II software.
Before adding to this page please review the following documents to learn more about Qsys or the known issues list:
- Qsys Handbook chapters listed on the Qsys Support page
- Quartus II Software Release Notes
- SOPC Builder to Qsys Migration Application Note 632
If you find an issue, please file a service request at mysupport so that it can be tracked and addressed by Altera: http://www.altera.com/mysupport
Formatting
If you find a new issue please add it to the list below by editing this page so that others can benefit from it as well. So that the formatting will be consistent, please use the Issue:Workaround format and provide short descriptive titles using the "Heading 3" format under the appropriate New Issues section.
New Issues
Qsys Editor (UI) Issues
Issue: Qsys doen't remember the user-entered IP search path (Tools -> Options ). Adding the user_components.ipx as described on page 6-6 doesn't work either. This usually occurs when launching Qsys outside a Quartus II project.
Workaround: add a <Path path=... /> entry into the main <$QUARTUS_INSTALLDIR>/sopc_builder/bin/root_components.ipx file.
Qsys Schematic Issues
Symbol Issues
Issue: No distinction between inputs and outputs - all signals for a given interface appear on one side. Unless the symbol file is opened (where inputs are represented as light blue crosses, while outputs are represented as purple crosses), one cannot make the distinction between signal types.
Workaround: None. For Qsys-generated symbols, the left-input right-output convention appliesy input/output interface, not by individual signal direction.
Other issues related to Block Symbol File (.bsf) symbols and lines were fixed beginning with the Quartus II software version 11.1.
Qsys Interconnect and Avalon Interface Issues
Native Addressing
Issue: Qsys does not support native addressing. Qsys will treat all natively address Avalon-MM slave interfaces as dynamically addressed 32-bit interfaces.
Workaround: Update any of your own natively addressed custom components to use dynamic addressing and include byte enables for the interface.
Merlin Address Routers for Custom peripherals
Issue: When generating the system, Merlin address routers are generated ignoring the ExplicitAddressSpan Avalon property. This causes channels to be greater than the complete address space in some cases; for instance, for a system that uses 29 bits of address space (512 MBs), with explicitly using only 16 MBs, Merlin address routers are generated with full 29 bits of address space per channel. Since the complete address space defaults to the size of the address space of the biggest addressable peripheral, this later causes errors in compilation (Verilog errors containing "...part-select direction is opposite from prefix index direction...") and also address space is overlapped with other peripherals with smaller address spaces.
Workaround: Manually edit nios_addr_router.sv files (there will be more of them; they are located under \{nios_name}\synthesis\submodules\ directory in your project directory) and manually set the values of the PADx variables to the desired address space size (ExplicitAddressSpanValue = 2^PADxValue). Do not change the value of the complete address space (RG variable), as this might introduce more problems.
Clock sources
Issue: Clocks generated in a subsystem can't be both exported and internally connected. Master interfaces associated with such clocks will cause problems when hierarchical systems are assembled. Exporting then re-importing these clocks will infer unnecessary clock-domain-crossing logic and latency.
Workaround: Anything that generates a global clock, e.g. an SDRAM controller or a PLL, should be instantiated in your top level system. Alternatively, consider using a clock bridge and exporting one side of the bridge.
Interrupts
Issue: When a tristate device has an interrupt, the BSP builder does not assign the interrupt correctly in system.h: it appears as -1. The QSYS output is actually correct as can be seen in the generated <designname>.sopcinfo. This issue has been assigned Altera internal SPR# 373680.
Workaround: Manually assign the interrupt in system.h after BSP generation in Nios II SBT.
Avalon-MM address space limit
Issue: The Avalon-MM bus specification is limited to 32-bit addressing. Attempting to generate a DDR3 memory controller with >4GB DIMM will fail. Qsys implementation of AXI interface is also limited to 32-bit addressing.
Workaround: None yet known.
SystemVerilog Interface support missing
Issue: Qsys does not support SystemVerilog interfaces. It is not possible to define a *_hw.tcl file for components that use interfaces.
Workaround: Use plain old ugly explicit ports like we did in the 90s.
Component (IP Core) Issues in Qsys
Unregistered Tri-state Inputs
Issue: Qsys does not support un-registered tri-state input signals
Workaround: Qsys automatically adds an input register to the return data path and compensates for this when upgrading designs that previously used unregistered tri-state inputs.
Component Editor Missing 'clken' definition for MM Slave
Issue: When building a Slave port to a Memory to connect as a Tightly Connected Data Memory, Qsys warns that a clock enable should be connected. However on the Component Editor Sigals Tab you can not select a 'clken' value for a MM Slave port.
Workaround: Manually edit the _hw.tcl file: e.g. add_interface_port ObjectMemory ClkEnOM clken Input 1
Java Error
Issue: Upon opening a Qsys file, the following error is given.
java.lang.StackOverError at com.altera.utilities.AltString.aintBlank(AltString.java:989) ...
Cause: A component in the same directory may have the same name (set_module_property NAME example in a CDF tcl file component_hw.tcl) as the Qsys file (example.qsys).
Workaround: Don't use the same Qsys design file name as that used by a component in the same directory.
Tri-state conduits and VHDL component
Issue: If you use a tri-state conduit, eg to a external Flash memory then get the VHDL component declaration from the Qsys "HDL Example" tab, it declares the chip enable, write enable and output enable signals as std_logic_vector(0..0). These DO NOT connect to the CPU entity declared in the verilog file.
Workaround: Change the component declaration to just use std_logic for these signals, then everything hooks up ok.
See http://www.alteraforum.com/forum/showthread.php?t=29684 for more details.
Wrong VHDL example in Qsys for different blocks
(Version: Quartus 11sp1)
Qsys is generating a faulty VHDL example. All lines like the following:
bus_ssram_tcm_write_n_out : inout std_logic_vector(0 downto 0) := (others => 'X'); -- ssram_tcm_write_n_out
Should be replaced by:
bus_ssram_tcm_write_n_out : inout std_logic := 'X'; -- ssram_tcm_write_n_out
Even if you use std_logic_vector(0 downto 0) as your top-level I/O's, there can be compilation errors, and worse some lines may be allays high / low or tristate. If a line is false connected, there are warnings (which are hard to find between the others) and you will see the problem in the RTL-Viewer.
This workaround is solving:
New Qsys Issues#Tri-state_conduits_and_VHDL_component
DDR2 SDRAM Controller with ALTMEMPHY Synthesis error
Nios II Issues Using Qsys
Using Nios II Processor for HardCopy designs
Issue: Using Nios II Processor for HardCopy designs results compilation error in Quartus II. You may encounter similar error message in Quartus II: "Error: <name> cannot use Memory Initialization File in a HardCopy device in a non-ROM operation mode"
Workaround: There is no workaround in Qsys. If you need to use HardCopy in your design, use SOPC Builder.
Nios Generation Fails on Ubuntu
Issue: NIOS generation fails using Quartus 11.0 on Ubuntu 11.04. This is caused by a missing locale.
Fix: sudo locale-gen en_US
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