Please publish I2C (OpenCores) as a QSys component.
There is a slight issue with the Qsys component. When arst_i is tied to a '1' if the FPGA is programmed and then in reset, the synchronous reset will not be seen until the clock starts up and the logic will not see a reset and will cause the SDA/SCL lines to remain in a '0' state until the synchronous reset is seen. The can be problematic on an I2C bus because if the lines happen to fall in a Start condition manner (i.e. SDA then SCL) the busy might be seen as busy and unless the SDA and SCL come back up in a stop condition (SCL then SDA) it may remain busy. Routing the arst_i out and connecting to the FPGA reset helped that. --Tmiddleton (talk) 14:53, 24 October 2013 (CDT)
2014/02/04 File i2c_opencores_sw.tcl has not been updated with ip new name
- .c and *.h has opencores_i2c basename instead new ip name i2c_opencores
Please post "i2c.h", "links.h" files, that were used in earlier versions of I2C OpenCores.